december 2006 rev 1 1/8 USBULC6-2F3 ipad? dual ultra low capacitance pr otection for high speed usb main application hi-speed usb port in wir eless handsets (up to 480 mb/s according to usb 2.0 high speed specification) features ultra low diode capacitance (1.2 pf max) two data lines (d+ and d-) protected against 15 kv esd breakdown voltage v br = 6.0 v min flip-chip 400 m pitch, lead-free very low leakage current very small pcb area rohs compliant description the USBULC6-2F3 is a monolithic, application specific discrete device dedicated to esd protection of high speed interfaces. its ultra low line capacitance secures a high level of signal integrity without compromizing the protection of downstream sensitive chips against the most stringently characterized esd strikes. benefits minimized impact on rise and fall times for maximum data integrity low pcb space occupation higher reliability offered by monolithic integration complies with the following standards: pin configuration (bump side) configuration order code tm: ipad is a trademark of stmicroelectronics iec 61000-4-2: 15 kv (air discharge) 8 kv (contact discharge) mil std 883g - method 3015.7 25 kv (human body model) part number marking USBULC6-2F3 eh flip-chip (4 bumps) b 1 2 a a2 a1 b2 b1 note: b1 and b2 bumps must be grounded on the pcb together www.st.com
characteristics USBULC6-2F3 2/8 1 characteristics figure 1. application diagram table 1. absolute maximum ratings (t amb = 25 c) symbol parameter value unit v pp esd discharge iec 61000-4-2, air discharge esd discharge iec 61000-4-2, contact discharge 15 8 kv p pp peak pulse power dissipation (8/20 s) 60 w t j maximum junction temperature 125 c t op operating temperature range -30 to + 85 c t stg storage temperature range -55 to +150 c table 2. electrical characteristics (t amb = 25 c) symbol parameter v br breakdown voltage i rm leakage current @ v rm v rm stand-off voltage v cl clamping voltage r d dynamic impedance i pp peak pulse current t voltage temperature coefficient v f forward voltage drop symbol test conditions min. typ. max. unit v br i r = 1 ma 6 9 v i rm v rm = 3 v 100 na r d exponential wave form 8/20 s, i pp = 1 to 5 a 1.6 ti r = 1 ma 5 10 -4 / c c line v line = 0 v, v osc = 30 mv, f = 1 mhz 1.2 pf i v i f i rm i pp v rm v f v br slope = 1/rd v cl usb connector vbus d- d + gnd b2 a2 b1 a1 b2 a2 b1 a1 to usb transceiver vbus d- d + gnd
USBULC6-2F3 characteristics 3/8 figure 2. eye diagram, board only (according to usb high speed) figure 3. eye diagram, board with USBULC6-2F3 (according to usb 2.0 high speed) board 480 mb/s horiz: 350 ps/div ver: 200 mv/div USBULC6-2F3 480 mb/s horiz: 350 ps/div ver: 200 mv/div figure 4. esd response to iec 61000-4-2 (+15 kv air discharge) figure 5. esd response to iec 61000-4-2 (-15 kv air discharge x: 50 ns/division y: 20 v/division 1 gs/s x: 50 ns/division y: 20 v/division 1 gs/s figure 6. junction capacitance versus frequency (typical values) figure 7. analog crosstalk measurements 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.e+07 1.e+08 1.e+09 c(pf) v osc =30 mv rms t j =25 c f(hz) 100.0k 1.0m 10.0m 100.0m 1.0g -120.00 -90.00 -60.00 -30.00 0.00 usbulc6 -2f3 db f (hz)
characteristics USBULC6-2F3 4/8 figure 9. digital crosstalk figure 8. s21 (db) attenuation measurements 100.0k 1.0m 10.0m 100.0m 1.0g -10.00 -8.00 -6.00 -4.00 -2.00 0.00 USBULC6-2F3 db f (hz) 10% 90% rise time = 1.647 ns v = 205 mv pkpk input: 1 v/div 0 mv offset 2 ns/div 5 gs/s output: 100 m v/div -300 mv offset 2 ns/div 5 gs/s figure 10. relative variation of peak pulse power versus initial junction temperature figure 11. peak pulse power versus exponential pulse duration 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0 25 50 75 100 125 150 p pp [t j initial] / p pp [t j initial=25c] t j (c) 10 100 1000 1 10 100 p pp (w) t j initial = 25 c t p (s)
USBULC6-2F3 ordering information scheme 5/8 2 ordering information scheme figure 12. clamping voltage versus peak pulse current (typical values, exponential waveform) figure 13. relative variation of leakage current versus junction temperature (typical values) 0.1 1.0 10.0 100.0 0 10203040506070 i pp (a) 8/20 s t j initial =25 c v cl (v) 1.e+00 1.e+01 1.e+02 25 50 75 100 125 i r [t j ]/i r [t j =25c] v r =3 v t j (c) usb ulc 6 - 2 f3 usb protection ultra low capacitance breakdown voltage number of lines package 6 = 6 v 2 = 2 lines f = flip-chip 3: min lead free, pitch = 400 m, bump = 255 m
package information USBULC6-2F3 6/8 3 package information figure 14. flip-chip dimensions figure 15. foot print recommendations figure 16. marking 0.92 mm 30 m 0.97 mm 30m 400 m 40 255 m 40 400 m 40 605 m 55 220m recommended 220m recommended 260m maximum solder stencil opening : copper pad diameter: solder mask opening: 300m minimum x y x w z w dot xx = marking yww = datecode (y = year ww = week) z = manufacturing location
USBULC6-2F3 ordering information 7/8 figure 17. flip-chip tape and reel specifications in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. note: more information is availa ble in the application notes: an2348: ?400 m flip-chip: package description and recommendations for use? an1751: "emi filters: recommendations and measurements" 4 ordering information 5 revision history dot identifying pin a1 location user direction of unreeling all dimensions in mm 4 +/- 0.1 8 +/- 0.3 4 +/- 0.1 1.07 1.02 1.75 +/- 0.1 3.5 +/- 0.1 ? 1.5 +/- 0.1 0.71 xxz yww xxz yww xxz yww part number marking package weight base qty delivery mode USBULC6-2F3 eh flip-chip 1.16 mg 5000 tape and reel (7?) date revision changes 15-dec-2006 1 initial release
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